I. Field of the Disclosure
The technology of the disclosure relates generally to standard library cells, and particularly to use and reuse of standard library cells to design logic circuits.
II. Background
Processor-based computer systems can include a vast array of integrated circuits (ICs). Each IC has a complex layout design comprised of multiple IC devices. Standard library cells are often employed to assist in making the design of such ICs less complex and more manageable. In particular, standard library cells provide a designer with pre-designed cells corresponding to commonly used IC devices that conform to specific design rules of a chosen technology. As non-limiting examples, standard library cells may include gates, inverters, multiplexers, and adders. Standard library cells corresponding to such IC devices in a standard library may include uniform complementary metal-oxide semiconductor (CMOS) base layers and base interconnects. For example, standard library cells corresponding to an inverter and a multiplexer may each include uniform base interconnects disposed on base p-type diffusion and base n-type diffusion regions that are configured to support n-type MOS (NMOS) and p-type MOS (PMOS) transistors, respectively. Thus, the standard library cells corresponding to the inverter and the multiplexer have compatible base designs, but differ with respect to layers added to the p-type and n-type diffusion regions and base interconnects.
In addition to standard library cells that correspond to certain IC devices, IC designs may include programmable cells commonly referred to as engineering change order (ECO) standard library cells. Such ECO standard library cells are employed as spare cells in IC designs, wherein the ECO standard library cells may be programmed after the IC design has been finalized for fabrication. Such programming is achieved by fabricating updated masks wherein corresponding layers of the ECO standard library cells have been altered to reflect design changes. As a non-limiting example, upon finalizing an IC design for fabrication, masks corresponding to the IC design are fabricated. However, the IC design may be altered following finalization so as to change certain properties of the IC design, such as the timing of signals or the functionality of a set of gates. Thus, the IC design may be changed to accommodate these changes by programming ECO standard library cells to function as a buffer for timing purposes or to function as an inverter to change the polarity of a signal to ensure a desired operation.
However, as fabrication technology size continues to decrease, the time and costs associated with programming ECO standard library cells and fabricating corresponding masks may increase. For example, programming ECO standard library cells at fabrication technology sizes of ten nanometers (10 nm) and below may involve altering multiple layers of the ECO standard library cells. Each layer that is altered may result in one or more masks being re-fabricated, which increases the corresponding time and costs of fabricating the IC. Therefore, it would be advantageous to employ ECO standard library cells as fabrication technology size continues to decrease while mitigating the time and costs associated with fabricating ECO standard library cells.